(59) Parallel Logic Simulator

	Machine:     Multi-PSI, PIM
	Environment: PIMOS, SIMPOS
	Language:    KL1, ESP
	Source Code: 0.4 MB
	Documents:   None

Overview

A VLSI-CAD tool to verify the logical and timing specification of designed circuits.

Purpose

Logic simulation is one of the most time-consuming stages in LSI design. We built a high-performance parallel logic simulator aiming at exploiting the entire potential of the Parallel Inference Machine with the Time Warp mechanism.

Specification

Signal and delay model: 3 values (Hi, Lo, X), non-unit delay
Input circuits: Circuits following the ISCAS'89 format
Input vectors: Randomly generated(The clock follows a given interval)

Configuration and Key features

This logic simulator consists of two parts: the preprocessing module and the simulation module.

In the preprocessing module, target circuits are statically partitioned according to the Cascading-Oriented Partitioning, which achieves low inter-PE communication, high parallelism extraction and load balancing.

In the simulation module, the Time Warp mechanism(TW) is used for time-keeping. It tries to exploit complete parallelism with speculative computation, while the rollback process cancels speculation errors to maintain the correctness of simulation.

The antimessage reduction mechanism, adequate message scheduling, and the Adaptively Moving Time-Ceiling are used to reduce the cost and frequency of rollback.

Bibliography

Y.Matsumoto and K.Taki. : Parallel Logic Simulator based on Time Warp and its Evaluation. In Proc. Int. Conf. on Fifth Generation Computer Systems, ICOT, Tokyo, 1992.

FTP

Parallel Logic Simulator [2,122K]

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