ABSTRACT 

Logic simulation, one of the most time-consuming stages in LSI design, is 
used to verify the logical and timing specifications of designed circuits. We 
built a high-performance parallel logic simulator capable of deriving a lot of 
parallelism from the target circuits so as to exploit the entire potential of 
large-scale MIMD machines, such as the PIM machine. 

KEY FEATURES 

Time Warp mechanism (TW) 
   TW asynchronously controls the order in which messages should be eval- 
   uated. It tries to exploit complete parallelism with speculative computa-
   tion, while the rollback process cancels speculation errors. 

Reduction of rollback overhead 
   The antimessage reduction mechanism, adequate message scheduling, and 
   the Adaptively Moving Time-Ceiling are used to reduce the cost and fre-
   quency of rollback. 

Cascading-Oriented Partitioning (COP) 
   COP provides high-quality solutions for circuit partitioning, achieving low 
   inter-PE communication, high parallelism extraction and load balancing. 



Process Flow

Paralle Logic Simulation




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