OVERVIEW 

The user specifies a behavioral specification, a structural specification, and con- 
straints on area and speed. Figure 1 shows an example. A behavioral specification 
(upper right) is specified in a hardware description language. A structural specifica-
tion (left) is specified in terms of a block diagram of the datapath. Constraints are ex-
pressed as inequalities in the gate count or propagation delay and transformed into op-
posite inequalities, or default NJs (lower right). One constraint on speed is highlight-
ed in each window, the corresponding path (left), the corresponding operation (upper 
right), and the corresponding default NJ (lower right). 




Figure 1. Inputs to co-LODEX 

co-LODEX divides the whole circuit to be designed into subcircuits. Each subcir-
cuit is designed by a design agent. co-LODEX divides the circuit so that the blocks 
along critical path candidates are distributed to as few agents as possible. It is likely 
that agents along a critical path candidate need a considerable amount of mutual com-
munication since agents sharing a constraint must communicate with each other. 

co-LODEX outputs a CMOS standard cell netlist that satisfies the constraints. The 
resulting netlist can be input to an automatic place-and-route system for CMOS stan-
dard cells. 


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