ABSTRACT 

CAD systems that can quickly produce quality designs are needed for the expand-
ing VLSI market. co-LODEX accepts constraints on area and speed, and outputs a 
CMOS standard cell netlist that satisfies the constraints. It can even obtain an exact op-
timal circuit for area or speed. Short turnaround is attained through the combination 
of parallel processing by several processors and their cooperation. 

KEY FEATURES 

Global optimization 
  An exact optimal circuit for area or speed can be obtained by iteratively strength-
  ening the corresponding constraint. 

Evaluation-redesign mechanism 
  Sufficient conditions for constraint violation, nogood justifications (NJs), are used. 

Cooperative design mechanism 
  Design agents exchange design results (in case of success) or NJs (in case of failure). 





Overview of co-LODEX 


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