ABSTRACT

Experimental circuit layout system development to prove the effectiveness
of FGCS paradigms. Generate a circuit layout diagram for a given circuit net
and a planned chip shape.

KEY FEATURES

Hierarchical Recursive Concurrent algorithm for placement and wiring.

Streamed parallel computation paradigm for system description.

Runtime co-operation to abut adjacent module layouts.

New Parallel wiring algorithm composed of a patterned-global and a maze-
local methods.

Time complexity: nearly O(N) N = no.of modules in the circuit.

Good speedup: nearly O(PE).


System Configuration




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